1. Field of the Invention
The present invention is directed to split-gate memory cells and semiconductor devices that include such memory cells. More particularly, the present invention is directed to split-gate memory cells in which the floating gate and the control gate are self-aligned with the control gate at least partially overlapping the control gate and a method of manufacturing such split-gate memory cells.
2. Description of the Related Art
Semiconductor memory cells utilizing floating gates that may be charged to alter the performance of the associated channel regions and control gates have been manufactured in a variety of configurations. Such memory cells are used in forming non-volatile memory arrays and devices, whereby stored data may be maintained for a relatively long period of time without consuming power or requiring frequent refreshing. Such devices are particularly useful in applications where power is unavailable for long periods or frequently interrupted or, in battery dependent applications, when low power consumption is desired.
As a result, these types of devices are frequently found in applications such as mobile communications equipment, memory blocks incorporated in microprocessor or microcomputer chips, and memories widely used for storing music and/or image data. The floating gate memory cells can be arranged in either split-gate or stacked gate configurations, and a combination of the two configurations may be included on a single device.
Split-gate memory cell transistors offer several advantages over conventional flash memories including bite operation (8 bit write/erase), relatively low programming currents of about 1 μA, good resistance to interference with the control gate used as the select transistor, and higher speeds provided by the use of hot carrier injection. Split-gate memory cell transistors also have several disadvantages including a larger size than a corresponding flash cell and lower endurance than a corresponding EEPROM (electrically erasable programmable read only memory) utilizing F-N (Fowler-Nordheim) tunneling injection.
A problem associated with the manufacture of floating gate memory cell arrays has been the alignment of the various functional elements including the source, drain(s), control gate(s), and floating gate(s). As the design rules for higher degrees of integration continue to decrease the size and spacing of these various elements, the need for precise and controllable alignment increases. The proper relative alignment and orientation of the various memory cell elements results in increased manufacturing yield, reduced performance distribution and increased reliability of the final semiconductor products.
Self-alignment is a well known technique in semiconductor manufacturing by which certain processing steps and the resulting structures are arranged and configured whereby certain elements, such as CMOS gate electrodes and the adjacent source/drain regions, are automatically aligned to one another as a result of the particular processing sequence, thereby avoiding the need to rely on the alignment of multiple photolithography patterns.
In the split-gate memory cell configuration, the control-gate field effect transistor (FET) plays a major role in determining the programming injection efficiency for source-side-injection cells. Good process control of the control gate length, Lcg, (which may also be referred to as the WL (word-line) poly length), i.e., the length of the control or select gate that is arranged over the channel region, can provide full turn-off of the control-gate device and reduce the likelihood of interference or disturbance during the programming of mirror cells.
A problem associated with the manufacture of split-gate memory cells can be a mismatch of the lengths and positioning of the paired control gates. As illustrated in FIG. 1, two control gates are arranged on either side of a common source region and over a portion of the channel between the source region and a corresponding drain region. If the control gate lengths Lcg1 and Lcg2 are not substantially identical, the amount of current flowing between the source and drain will be different and the operation of the two mirror cells will differ accordingly.
Data may be stored in such a split-gate memory cell by utilizing the changes in the current flowing through the respective transistors as a function of the status of the floating gates 104a as charged (program) or discharged (erase). During a charging (program) operation, electrons can be injected into the floating gate 104a by, for example, applying a relatively high voltage, e.g., 8–12 V, to the common source, an intermediate voltage, e.g., 1–3 V, to the corresponding control gate 120, and a relatively low voltage, e.g., 0–0.5 V, to the corresponding drain 126, while holding the substrate near ground, 0 V. As the floating gate 104a accumulates electrons via the resulting channel hot electron injection (CHEI) mechanism, the effective threshold voltage, Vth, of the transistor will increase, typically to a level above about 3 V.
Conversely, during a discharging (erase) operation electrons can be withdrawn from the floating gate 104a by, for example, applying a relatively high voltage, e.g., 8–12 V, to the control gate 120 while holding the common source 116, the corresponding drain 126 and the substrate 100 at or near ground, 0 V. As the floating gate 104a discharges its accumulated electrons via the resulting Fowler-Nordheim (F-N) tunneling mechanism, the effective threshold voltage, Vth, of the transistor will decrease, typically to a level below about 1 V and may even decrease to a level below 0 V.
Once programmed or erased, the split-gate memory as illustrated in FIG. 1 may be read by applying a read voltage of about 2 V to the control gate 120, applying about 1 V to the drain 126, and holding the source 116 and the substrate 100 at or near ground, 0V. If the floating gate is charged when read, the Vth will be sufficiently above the read voltage that the transistor will remain “off.” Conversely, if the floating gate is discharged when read, the Vth will be sufficiently below the read voltage to ensure that the transistor will be “on.” As will be appreciated, the sizing and doping of the split-gate transistor elements, selected in consideration of the performance requirements for the final semiconductor product, will determine the precise ranges of voltages and currents required to operate such a transistor.
As shown in FIG. 1, a split-gate memory cell has a structure wherein the floating gates 104a and the corresponding control gates 120 are arranged on opposite sides of a common source region 116 and separated from each other by insulating material(s). The floating gates 104a are also electrically insolated by the surrounding insulating materials from external current sources.
The insulating material 200 between the substantially vertical portions of the floating gate 104a and the control gate 120 may be referred to as an intergate insulating layer, tunneling insulator or tunneling oxide. The insulating material 204 between the floating gate 104a and the substrate 100 may be referred to as the coupling insulator or coupling oxide. Similarly, the insulating material 206 between the control gate 120 and the substrate 100 may be referred to as the gate insulator or gate oxide.
The insulating materials 204 and 206, for example, may be formed at different stages during the manufacturing process and may, therefore, be somewhat different in composition and/or thickness. The insulating material 202 between the upper side of the floating gate 104a and the control gate 120 may be referred to as the interpoly oxide (IPO).
Each of these insulating regions 200, 202, 204, 206, will, in turn, have an associated capacitance, i.e., Ctun, CIPO, Cc, Cg, that contributes to a total capacitance Ctot for the split-gate transistor. These capacitances will also affect the voltage that can be applied to the floating gate 104a to produce the electrical field that, in turn, produces and directs the hot electrons to the floating gate during the charging (program) operation. During the program step, the voltage Vfg induced at the floating gate 104a will generally correspond to the voltage applied to the common source Vs according to equation I.Vfg=Vs*(Cc/Ctot)   I
Accordingly, the magnitude of Cc/Ctot is a factor that must be considered when designing a split-gate transistor. Higher values of Cc/Ctot allow higher voltages to be induced in the floating gate, thereby increasing the electron injection (program) efficiency of the transistor.
Similarly, during a discharge (erase) operation, the electrons move from the floating gate to the control gate by F-N tunneling through the tunnel insulating layer 200 and/or the interpoly oxide 202. In this case, the voltage Vfg induced at the floating gate 104a will generally correspond to the voltage applied to the control gate Vcg according to equation II.Vfg=Vcg*((Ctot−CIPO−Cg)/Ctot)   II
Accordingly, for improved performance, it is desirable to increase CIPO, thereby decreasing the effective voltage on the floating gate Vfg. Decreases in Vfg during discharge operations will affect the endurance characteristics of the memory cell as well as the electron discharge (erase) efficiency. Further, when utilizing the F-N tunneling mechanism, the tunnel current can be reduced by electron traps within the insulating layers, thereby degrading device performance. This degradation can be suppressed somewhat by increasing the effective voltage of the floating gate.
The relationship between the capacitance contributions of the tunneling Ctun and interpoly oxide CIPO to the behavior of the floating gate can also be expressed as a coupling ratio α according to formula III.α=((Ctun+CIPO)/Ctot)   III
Certain manufacturing processes and the resulting floating gate structures, are illustrated and described in U.S. Pat. Nos. 6,329,685; 6,362,048; 6,429,472; 6,486,508; 6,524,915; 6,562,673 and 6,589,842, as well as U.S. Patent Application No. 2002/0034846, and are incorporated herein by reference, in their entirety.